Integrated circuit (IC) chips (e.g., “chips”, “dies”, “ICs” or “IC chips”), such as microprocessors, coprocessors, and other microelectronic devices often use package devices (“packages”) to physically and/or electronically attach the IC chip to a circuit board, such as a motherboard (or motherboard interface). The die is typically mounted within a package that, among other functions, enables electrical connections between the die and a socket, a motherboard, or another next-level component. As die sizes shrink and interconnect densities increase, such electrical connections require scaling so as to match both the smaller pitches typically found at the die and the larger pitches typically found at the next-level component.
An existing approach to interconnect scaling within microelectronic packages is to use a single high density interconnect (HDI) substrate to handle the space transformation from die bump pitch, where a typical pitch value may be 130-150 micrometers (microns or μm) to system board level (e.g., motherboard) pitch, where a typical pitch value may be 400 micrometers, i.e., 0.4 millimeter (mm). This approach results in very fine line, space, and via design rules to enable die routing and very large substrate body sizes in order to interface at the system board level pitch.
For certain devices, such as tablet computers, cell phones, smart phones, and value phone devices, it may be desirable to use a smaller die or IC chip footprints. For those devices it may also be desirable to use a low height IC chip packaging, such as a “low Z-height package”. However, current IC chip packages and motherboard mounting technologies suffer drawbacks, such as increased Z-height, increased cost, reduced manufacturing rate, and specialized equipment requirements, as compared to improved processes and devices described herein.